SegaXtreme

Where	Original text	Correction
p. (6), 33 and 47	"Erase/Write Upper-Right Coordinate Register"	"Erase/Write Lower-Right Coordinate Register"
p. 23 and 58	"TVHR"	"TVMR"
p. 37 and 134 Table "Screen Modes" Lines where column "Name" contains "Normal", "Rotation 16", "Rotation 8"	Column "Resolution" contains : "320x224 320x240 352x224 352x240"	Column "Resolution" contains : "320x224 320x240 352x224 352x240 640x224 640x240 704x224 704x240"
p. 39	"Set the value of the VBE and FCT bits to “0.”"	"Set the value of the VBE, FCM, and FCT bits to “0”."
p. 39	"Manual erase/write of the frame buffer is specified by writing “0” to the VBE, FCM and FCT registers."	"Manual erase/write of the frame buffer is specified by writing “0” to the VBE and FCT registers and “1” to the FCM register."
p. 40	"If the timing for frame change is known in advance as in normal, high resolution, and interlace, specify erase & change and perform erase/write during the display period. In this case, erase/write of the entire display screen is possible."	"If the timing for frame change is known in advance in normal or high resolution screen modes, specify erase then change and perform erase/write during the display period. In this case, erase/write of the entire display screen is possible."
p. 40	"7) Return VBE to “0” after the V-blank OUT interrupt to stop V-blank erase."	"7) Return VBE to “0” after the V-blank OUT interrupt to prevent V-blank erase to occur automatically in the next V-blank."
p. 46	"When parts are written to the frame buffer, the VDP1 automatically erases the frame buffer."	"VDP1 can erase automatically the display frame buffer while writing parts to the draw frame buffer."
p. 49	"The number of pixels required for V-blank erase is expressed by (X3 – X1 + 1) x (Y3 – Y1 + 1) x 8"	"The number of pixels required for V-blank erase in a 16 bpp frame buffer is expressed by (X3 – X1) x (Y3 – Y1 + 1) x 8"
p. 49	"The number of pixels that can be used in V-blank erase is given by"	"The number of pixels that can be used in V-blank erase in a 16 bpp frame buffer is given by"
p. 50	"Table 4.5 Number of Pixels that Can Be Used in V-Blank Erase (in Non-Interlace Display)"	"Table 4.5 Number of Pixels that Can Be Used in V-Blank Erase in a 16 bpp frame buffer (in Non-Interlace Display)"
p. 62	"If RGB code, MSB = 0. If color bank code, MSB = 0 if RGB code is mixed, and MSB can be either 0 or 1 if RGB is not mixed. Set MSB to match data processing by the VDP2."	"If the frame buffer can use RGB codes (see Sprite color mode bit, p. 207 of VDP2 User's Manual), RGB codes MSB must be set to 1 and color bank code MSB must be set to 0. If the frame buffer is all in palette format, set MSB according to its use by VDP2 (see Sprite types, p. 200 of VDP2 User's Manual)."
p. 79	"Clipping Mode Bit (Clip): bit 10"	"User Clipping Enable Bit (Clip): bit 10"
p. 79	"User Clipping Enable Bit (Cmod): bit 9"	"Clipping Mode Bit (Cmod): bit 9"
p. 84 Figure 6.7 Drawing Area	"Upper-right coordinate of user clipping"	"Upper-left coordinate of user clipping"
p. 90 and 91	"Because the draw pixel data is color bank code, color calculation cannot be performed."	"Color calculation can be executed when the color code is color bank code, but for other modes than replace and shadow, on-screen results depend on the ordering of VDP2 color RAM."
p. 93	"Except for color calculation of replace and shadow, color calculation can only be performed when the color code of the original picture is RGB code. Color calculation can be executed when the color code is color bank code, but the results are not guaranteed."	"Except for color calculation of replace and shadow, color calculation can only be fully determined by VDP1 when the color code of the original picture is RGB code. Color calculation can be executed when the color code is color bank code, but on-screen results depend on the ordering of VDP2 color RAM."
p. 94 and 148 Unnamed table Lines where column "Background MSB" contains "0"	Column "Background" contains "Not restricted".	Column "Background" contains "Palette".
p. 96 Figure "Examples of Color Calculation" Drawing under "Color Calculation mode= 3"	"Half-Luminance"	"Half-Transparent"
p. 97	"The color code is valid only when the frame buffer is color bank code (this is because the MSB is used for shadow enable and window enable in the VDP2, eliminating an RGB recognition bit), thus making it impossible to perform color calculation. Specify replace for color calculation."	"On-screen results are guaranteed only when the frame buffer is all in palette format (see Sprite color mode bit, p. 207 of VDP2 User's Manual). This is because the sprite pixels MSB is used for shadow or window processing by VDP2, instead of an RGB recognition bit."
p. 105	"Vertex (B), X coordinates (XA); or display, X width (XB)"	"Vertex (B), X coordinates (XB); or display X width (XB)"
p. 105	"Vertex (B), Y coordinates (YA); or display, Y width (YB)"	"Vertex (B), Y coordinates (YB); or display Y width (YB)"
p. 105	"Extend the code with the upper 6 bits."	"Extend the code to the upper 5 bits."
p. 159	"Set the lower 2 bits of lookup tables to “00.”"	"Set the lower 2 bits of lookup table address to “00”."
p. 159	"When the frame buffer is set to 8 bits/pixel, set the MSB ON bit (MON) to “1.”"	"When the frame buffer is set to 8 bits/pixel, set the MSB ON bit (MON) to “0”."

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		mrkotfw		Apr 9, 2020
			Thank you for this. Curious, how were the errors regarding the frame erase/change found?

		fafling		Apr 9, 2020
			Explanations in the same order as the table : p. 39 : incoherent with tables on p. 38 and 41. p. 40 : erase/write during the display period is possible for frame buffer of type normal or high resolution and doesn't depend on interlacing as explained on p. 49. Erase & change is V-blank erase, so it only erases during V-blank, not during the display period. To do that, you have to alternate between erase setting then change setting as illustrated in table p. 41. p. 40 : setting VBE to 0 after V-blank OUT doesn't stop V-blank erase, it's already stopped by the beginning of the display period. But if it remains at 1, V-blank erase will start again when the display period ends as explained in the paragraph "Erase & Change (Manual Mode)" on the same page. p. 46 : Sega failing to explain why Erase/write is called that way. VDP1 controls 2 frame buffer buses as can be seen on the service manual of the console : one bus writes on the draw frame buffer, while the other reads and optionally erases the display frame buffer. The result of that read is streamed to VDP2, in sync with the display, via the VDP1/VDP2 communication channel also visible in the service manual. This hardware configuration also explains why it is VDP1 that performs the affine transformation of the display frame buffer if specified on VDP2 and if the frame buffer is of type rotation 8 or 16 : VDP2 has no bus that connects to VDP1 frame buffers. VDP2 sends the transformation parameters via the communication channel, and VPD1 reads the display framebuffer accordingly. In that case, the read is no longer sequential and probably slower, explaining why VDP1 can't erase a frame buffer of type rotation during the display period, only during V-blank.

		mrkotfw		Apr 11, 2020
			pg. 39 where it says "Set the value of the VBE and FCT bits to "0.", it should be "Set the value of the VBE, FCM, and FCT bits to "0."

		mrkotfw		Apr 11, 2020
			Shouldn't the correction on pg. 40 where it's written: "If the timing for frame change is known in advance in normal or high resolution screen modes, specify erase then change and perform erase/write during the display period. In this case, erase/write of the entire display screen is possible." Shouldn't that be erase & change? What it's saying is to specify erase & change at VBLANK, then at VBLANK-OUT, specify just erase/write.

		fafling		Apr 11, 2020
			I add this to the errata : Your correction of p.39. "Erase/Write Upper-Right Coordinate Register" on p. (6), 33 and 47. The formula for the fill area of erase/write in p. 49 : according to the conversion of the registers X1 and X3 in actual coordinates, the detailed formula is actually ((X3 x 8 - 1) - (X1 x 8) + 1) x (Y3 – Y1 + 1), simplified to (X3 – X1) x (Y3 – Y1 + 1) x 8. The fact that the number of pixels computed in p. 49-50 is for a 16 bpp frame buffer. In a 8 bpp frame buffer, the registers X1 and X3 are multiplied by 16 instead of 8, so the fill area is (X3 – X1) x (Y3 – Y1 + 1) x 16. And VDP1 erases 2 pixels at a time (p. 46), so the number of pixels of table 4.5 are doubled. The drawing p. 84. As I understand VDP1 manual (it is unfortunately unclear on that subject), erase/write can only be started at 2 points in time, v-blank in (Erase & Change setting at v_blank in, erase/write starts immediately) or v-blank out (1-Cycle Mode setting where erase/write starts each v-blank out, or Erase setting at v-blank out and erase/write starts at next v-blank out), and lasts to the next v-blank out. Since Erase & Change setting only erases the display frame buffer during v-blank, it will not always erase the whole display area of the frame buffer (although it is possible for an rotation 8 framebuffer). Only the 1-Cycle Mode or Erase settings guarantee the complete erasure of the display area of non rotation frame buffers, but Erase setting has to be set 2 frames before the frame buffer switch.

		fafling		Aug 28, 2020
			Added TVMR register misspelled as TVHR on p. 23 and 58.

		fafling		Oct 17, 2021
			VDP1 and VDP2 manuals with fixes : Sega Saturn Technicals Docs Fixed...