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The bus width is determined by the number of data lines. E.g. for the A-bus, the diagram in your picture lists 16 data lines (AD0-AD15) and 26 address lines (AA0-AA25). So the bus has a 2^26 bytes, or 64MB address space, and can transfer 16 bits at a time. 32-bit transfers will be split up into two consecutive 16-bit transfers.
The B-bus is different in that it's some kind of multiplexed or packet-oriented bus, there's no separate address and data lines, just BD0-BD15 and some control lines. The bus also has devices with all 16 lines (VDP1, VDP2), and only 8 (SCSP). I have a vague memory it might be described in some patent, but I couldn't find the file now. |