I'm trying to setup UBC in order to make it triggering at the beginning of BUP_Init function :
Code: | | | /* UBC setup : address we want to hook. */ BARA = (unsigned long)BUP_LIB_ADDRESS; /* UBC setup : address mask. */ BAMRA = 0; /* No address mask. */ /* UBC setup : break condition. */ BBRA = BBR_CPA_CPU | BBR_IDA_INST | BBR_RWA_READ | BBR_SZA_WORD; /* UBC setup : break cycle. */ BRCR = BRCR_CMFCA | BRCR_UMD; /* Set interrupt trampoline. */ unsigned int* vbr = (unsigned int *)asm_int_vector_base_get(); vbr[0x0C] = (unsigned int)asm_bup_init_start_ihr; asm_intc_enable(); |
with the following UBC definitions :
Code: | | | /*---------------------- BARA: 0xFFFFFF40 ----------------------*/ #define BARA (*(volatile unsigned long *)(0xFFFFFF40)) #define BARB (*(volatile unsigned long *)(0xFFFFFF60)) /*---------------------- BAMRA: 0xFFFFFF44 ----------------------*/ /* Set to 0h : No BARA bits are masked, entire 32-bit address is included in break conditions * Set to 1h : Lower-order 10 bits of BARA are masked * Set to 2h : Lower-order 12 bits of BARA are masked * Set to 3h : 1 All BARA bits are masked; */ #define BAMRA (*(volatile unsigned long *)(0xFFFFFF44)) #define BAMRB (*(volatile unsigned long *)(0xFFFFFF64)) /*---------------------- BBRA: 0xFFFFFF48 (word access) ----------------------*/ #define BBRA (*(volatile unsigned short *)(0xFFFFFF48)) #define BBRB (*(volatile unsigned short *)(0xFFFFFF68)) #define BBR_CPA_NONE (0 << 6) #define BBR_CPA_CPU (1 << 6) #define BBR_CPA_PER (2 << 6) #define BBR_IDA_NONE (0 << 4) #define BBR_IDA_INST (1 << 4) #define BBR_IDA_DATA (2 << 4) #define BBR_RWA_NONE (0 << 2) #define BBR_RWA_READ (1 << 2) #define BBR_RWA_WRITE (2 << 2) #define BBR_SZA_NONE (0 << 0) #define BBR_SZA_BYTE (1 << 0) #define BBR_SZA_WORD (2 << 0) #define BBR_SZA_LONGWORD (3 << 0) /*---------------------- BRCR: 0xFFFFFF78 (word access) ----------------------*/ #define BRCR (*(volatile unsigned short *)(0xFFFFFF78)) #define BRCR_CMFCA (1 << 15) #define BRCR_CMFPA (1 << 14) #define BRCR_EBBA (1 << 13) #define BRCR_UMD (1 << 12) #define BRCR_PCBA (1 << 10) #define BRCR_CMFCB (1 << 7) #define BRCR_CMFPB (1 << 6) #define BRCR_SEQ (1 << 4) #define BRCR_DBEB (1 << 3) #define BRCR_PCBB (1 << 2) |
Purpose of this is to retrieve pointer to BupConfig structure, stored in R6.
In some games, UBC seems to trigger at wrong timining : It does trigger, but with wrong value in R6 register.
This problem happens randomly : it may trigger at expected timing on 10th try while other tries triggered, but with incorrect R6 value.
Any idea ? (SH2 cache side effect ??) (UBC not correctly configured ?) |
