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A-Bus CS2 |
srg320 - Jul 9, 2021 |
antime | Jul 9, 2021 | |||
SCU errata 32 says that reads from the A- and B-bus areas always generate a 4-byte read, which I ran into when designing the USB cartridge. It is curious there is a region that works differently. |
tpu | Nov 7, 2022 | |||
Some test about ABUS-CS2: you can't set wait cycles from ASR1 register. But ADDR[18-15] set the wait cycles. |
Jowaco | Aug 19, 2024 | |||
I’m looking for similar info and came across your post. I’ve been digging through some old SCU docs and noticed the same thing with the A-Bus CS2. It’s odd how the BIOS uses different addresses for 16-bit and 32-bit data. I didn’t find much in the manuals either, but I did see some info on skin.land... where they talked about these quirks. It might be worth a look if you’re still into this topic. |