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VDP2 Transparency Issue
a-dac - Jul 16, 2005

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    mrkotfw Jul 31, 2005 
i would really really like to see what you have changed! could you please upload a tar ball of what you've changed? i want to learn from my mistakes!

    a-dac Jul 31, 2005 
Here are the changed files.. the map, cel & pal files are from the original demo. There are corrupt tiles on the right and bottom from the way Cel2VRAM writes the tiles to ram, i'll leave that to you to change. I may be missing some register setting but the controller tiles are displayed so it should give you a better start. From your old source it lookes like your main problem was the rsgisters that point to where the map and tiles are were pointing to the wrong spot. Thats why I used NBG0 because I have played with that more than NBG2 or 3. Hope this helps.

    mrkotfw Jul 31, 2005 
thank you again, i'll look over the changes. looks like i missed a few things, mostly the `PRINA' and `PRINB' registers. what i really don't understand is the cycle pattern registers, could you somehow explain to me how it works? :cheers

    a-dac Jul 31, 2005 
The PRINA & PRINB Regs probably aren't needed for one background. The timing regs are simple use the VDP2 manual as a reference. In your demo the VRAM is partitioned into 4 banks A0, A1, B0, & B1 by bits 8-9 in RAMCTL so we set CYCA0, CYCA1, CYCB0 & CYCB1. If we only partitioned the VRAM into A & B then we would use CYCA0 and CYCB0. Table 3.5 in the manual shows the access commands, so where ever you are storing your tiles in ram you need to put the proper access command in the correct CYCxx register.

Use your vdp2 demo as an example:

CYCA0 = 0x0FFFFFFF; // VRAM A0 - 0 = NBG0 Pattern Name Data

CYCA1 = 0xCFFFFFFF; // VRAM A1 - C = NBG0 Vertical Cell Scroll Table (C probably not needed)

CYCB0 = 0x44FFFFFF; // VRAM B0 - 4 = NBG0 Character Pattern Data

CYCB1 = 0xFFFFFFFF; // VRAM B1 - Nothing used in this ram area

in CYCB0 we put in 2 0x4's by refering to table 3.3. For 256 colors, 2 VRAM access are required. So if we were using 32,768 colors we would change CYCB0 to 0x44FF44FF;

The 0xFF's between the four timings are from table 3.4. Since the first two 4's are in T0-T2, the second set must be in T4-T7. (At least thats how I understand it).

Hope this gives you a little more understanding and hasn;t confused you even more.

As I said before this is just my take on how it works.

    mrkotfw Jul 31, 2005 
i'm assuming this is somewhat correct: Code: 
  
/* -*- mode: c; tab-width: 4; -*- */ #include "misc.h" #include "nbg2.h" #include "regs.h" #include "sclf.h" #include "vdp2.h" #define NBG2_CEL (VDP2_VRAM_A0 + 0x40000) #define NBG2_MAP VDP2_VRAM_A0 #define NBG2_COL VDP2_CRAM int ss(void) { struct vdp2_t *vdp2 = (struct vdp2_t *)VDP2; vdp2->reg[TVMD] = 0x0000; sclf_cel_vram(gpad_cel,(void *)NBG2_CEL,31808); sclf_map_vram(gpad_map,(void *)NBG2_MAP,32,24,0,256); sclf_pal_cram(gpad_pal,(void *)NBG2_COL,256); vdp2->reg[PRINB] = N2PRIN; vdp2->reg[BGON] = BIT(2); vdp2->reg[CHCTLB] = BIT(1); vdp2->reg[PLSZ] = 0x0000; vdp2->reg[PNCN2] = BIT(14) | BIT(15); vdp2->reg[MPABN2] = 0x0000; /* VDP2_MAP(NBG2_MAP,NBG2_MAP); */ vdp2->reg[MPCDN2] = 0x0000; /* VDP2_MAP(NBG2_MAP,NBG2_MAP); */ vdp2->reg[RAMCTL] = BIT(8) | BIT(9); vdp2->reg[CYCA0U] = 0x0FFF; vdp2->reg[CYCA0L] = 0xFFFF; vdp2->reg[CYCA1U] = 0xCFFF; vdp2->reg[CYCA1L] = 0xFFFF; vdp2->reg[CYCB0U] = 0x44FF; vdp2->reg[CYCB0L] = 0xFFFF; vdp2->reg[TVMD] = BIT(15); while(1) { vdp2_vblank(vdp2); } return 0; } /* EOF */
okay, i changed it to: Code: 
  
 vdp2->reg[CYCA0U] = 0x1FFF; vdp2->reg[CYCA0L] = 0xFFFF; vdp2->reg[CYCA1U] = 0xFFFF; vdp2->reg[CYCA1L] = 0xFFFF; vdp2->reg[CYCB0U] = 0x66FF; vdp2->reg[CYCB0L] = 0xFFFF;

   mrkotfw Aug 4, 2005 
new post, i just got my pc comms link so i may get it to work under linux/freebsd! :cheers

    mrkotfw Aug 15, 2005 
i just recieved my db25 cable and my hacks for sat works! i haven't tried it on linux, but it works perfectly on freebsd!


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